5/28/2023 0 Comments Cpuinfo 4620Currently this channel can reveal supervisor data in the L1 cache and the contents of recent stores. This issue has been assigned CVE-2020-24512 and is rated Low.ĬVE-2020-24513: Information Disclosure on Some Intel Atom ProcessorsĪ potential domain bypass transient execution vulnerability was discovered on some Intel Atom® processors that uses a microarchitectural incidental channel. It may be possible for a local attacker to distinguish some cases of trivial data-cache-lines from non-trivial data cache-lines by inferring cache state using cache timing methods. Such optimizations may lead to changes in cache-allocation or write-back behavior for such cache-lines. This issue has been assigned CVE-2020-24511 and is rated Moderate.ĬVE-2020-24512: Observable Timing Discrepancy in Some Intel ProcessorsĬertain optimizations on some Intel processors target „trivial data value” cache-lines, such as all-zero value cache-lines. As a consequence, this issue may allow an authenticated user to potentially enable information disclosure via local access. Microcode misconfiguration in some Intel processors may cause EIRBS (Enhanced Indirect Branch Restricted Speculation) mitigation ( CVE-2017-5715) to be incomplete. IPAS: Security Advisories for June 2021ĬVE-2020-24511: Improper Isolation of Shared Resources in Some Intel Processors.This issue has been assigned CVE-2020-24489 and is rated Important. The highest threat from this vulnerability is to data confidentiality and integrity as well as system availability. Entries from the context cache on some types of context cache invalidations may not be properly invalidated which may allow an authenticated user to potentially enable escalation of privilege via local access. Background Security Issues CVE-2020-24489: VT-d-related Privilege EscalationĪ potential security vulnerability in some Intel® Virtualization Technology for Directed I/0 (VT-d) products was found. Please contact your hardware vendor to determine whether more recent BIOS/firmware updates are recommended, as additional improvements may be available. Red Hat provides updated microcode, developed by our microprocessor partners, as a customer convenience. Red Hat is aware of several CPU hardware flaws that affect Intel CPU hardware microarchitecture and on-board components. Intel Microcode Updates That Mitigate The Issues.Transactional Synchronization Extension (TSX) Deprecation.Intel® Turbo Boost Max Technology 3.0 (ITBM) Turbo Ratio Limit (TRL) Overreporting.External Node Controller (XNC) Coherency Issue.
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